1. Field of the Invention
The present invention relates to a reticle, and a method of laying out wirings and vias.
2. Description of the Related Art
Recently, with the miniaturization of semiconductor devices, there is a demand for reduction in a distance between wirings to increase a wiring density (see Japanese Patent Application Laid-open No. 2005-19604; hereinafter, referred to as Patent Document 1). In response to such a demand, it is necessary to increase a degree of integration even for vias which are formed for the connection between the wirings in upper and lower wiring layers. On the other hand, if the degree of integration is increased by the miniaturization of an element, it becomes difficult to form the vias as designed in some cases.
FIG. 4 illustrates an example of a conventional method of laying out the wirings and the vias. In FIG. 4, a first wiring layer including first wirings 103 and a second wiring layer including second wirings 105 are illustrated. Each of the first wirings 103 and the second wirings 105 is provided along at least one of a first direction and a second direction which perpendicularly cross each other. In such a wiring structure, the vias are arranged to allow a wiring pitch and a via pitch to have the same minimum size. Each side of the rectangular via is arranged to be parallel to or perpendicular to the first and second wirings. If a large number of vias are provided to be close to each other in such a via arrangement, it becomes difficult to resolve a via opening pattern due to the increased degree of integration for the formation of the via opening pattern by light exposure using photolithography. Moreover, even if the via opening pattern is resolved, a resist between the vias loses its shape to increase a frequency of occurrence of a short between the vias during an operation of the semiconductor device. For example, as illustrated in FIG. 6, when the distance between the vias is small, via holes 107 link together after development in some cases. As a result, the short between the vias disadvantageously occurs in an area where the vias are formed at a high density, during the operation of the semiconductor device. Further, the deformation of the via occurs to obstacle the burial of a wiring material.
As one of the reasons for the occurrence of the problem as described above, the following fact is given. In a via hole formation step by the photolithography, a distance between the via opening patterns on a reticle becomes smaller as compared with a light wavelength used for the light exposure. When the patterns of vias or wirings at a high density are to be formed by the photolithography, an optical interference phenomenon is used. By using an optical interference effect between the via patterns or the wiring patterns, an effective contrast ratio can be increased as illustrated in FIG. 7. Therefore, a resolving power can be increased. If the distance between the via opening patterns is smaller than the light wavelength used for the light exposure, it becomes difficult to resolve the neighboring via opening patterns. As the via opening patterns becomes closer to each other, this tendency becomes more remarkable. The reason for this is as follows. When the distance between the neighboring via opening patterns is smaller than the light wavelength used for the light exposure, diffracted waves come closer to each other as illustrated in FIG. 8, resulting in a smaller amplitude of a composite wave. As the via opening patterns become closer to each other, the amplitude of the composite wave becomes smaller. As a result, the effective contrast ratio is lowered. Therefore, as the via opening patterns become closer to each other, there is a point at which each of the via opening patterns is no longer satisfactorily resolved. If the resolution is insufficient, there is a fear that even a part which is not desired to be dissolved is disadvantageously dissolved at the time of development of the via opening patterns on the resist after the light exposure. As a result, the via shape is sometimes deformed to result in the occurrence of the short between the vias in the worst case. Furthermore, when the via shape is deformed even if the via is successfully resolved, there is a fear that an initial breakdown voltage during the operation of the semiconductor device may be lowered. As a result, a yield and a reliability of the semiconductor device are lowered in some cases. For the reason as described above, there is a demand in terms of a process that the distance between the vias is increased as much as possible when the distance between the via opening patterns is smaller than the light wavelength used for the light exposure.
As the arrangement for allowing the distance between the vias to be increased as much as possible, there is an arrangement as described in Japanese Patent Application Laid-open No. 2005-268748 (hereinafter, referred to as Patent Document 2), for example. Patent Document 2 describes a construction in which the zigzag arrangement of the vias allows the minimum pitch size for contacts to be larger than the minimum wiring size in a multi-layered wiring structure including lower wirings and upper wirings deposited thereon and via contacts for connecting the lower and upper wirings, as shown in FIG. 5. In Patent Document 2, the structure described above can ensure a certain process margin in the contact formation.
With the further miniaturization in recent years, however, the minimum distance between the vias is further reduced. Therefore, even when the vias are arranged as illustrated in FIG. 5, there still exist the problems such as the via deformation and the occurrence of the short between the vias which constitutes one of the reasons for failure occurring during the operation of the semiconductor device. Therefore, there is a fear that incomplete burial of the via or a reduction in yield of products may be brought about. In order to remedy the problems as described above, the arrangement with a further larger distance between the vias advantageously acts on the resolution, the short between the vias, the via deformation, and the like. On the other hand, when the distance between the vias is increased, there arises another problem of a lowered degree of integration of the vias.